Add the values in registers b and c, store the result in register a.
Add the value in register b and the value im, store the result in register a.
Bitwise AND the values in registers b and c, store the (integer) remainder in register a.
Bitwise AND the value in registers b and the value im, store the (integer) remainder in register a.
An assembler code sequence.
An assembler code sequence. Includes comments and labels.
Machine instructions.
If the Z condition code is set, set the program counter to its value plus four times disp.
If the N condition code is clear, set the program counter to its value plus four times disp.
If both of the Z and N condition codes are clear, set the program counter to its value plus four times disp.
If either of the Z or N condition codes is set, set the program counter to its value plus four times disp.
If the N condition code is set, set the program counter to its value plus four times disp.
If the Z condition code is clear, set the program counter to its value plus four times disp.
Set the program counter to its value plus disp.
Set R31 to the value of the program counter plus one.
Abstract interface for all branch instructions.
If register a contains a value that is negative or greater than or equal to the value im, set register a to zero.
Set the Z condition code if the contents of registers b and c are equal.
Set the Z condition code if the content of register b and the value im are equal, otherwise clear Z.
A machine code sequence.
Comment
Divide the values in registers b and c, store the (integer) result in register a.
Divide the value in register b and the value im, store the (integer) result in register a.
Operand types
Load register a with the byte value stored in memory at the address given by the contents of register b plus the value im.
Load register a with the word value stored in memory at the address given by the contents of register b plus the value im.
Divide the values in registers b and c, store the (integer) remainder in register a.
Divide the value in registers b and the value im, store the (integer) remainder in register a.
Shift the value in register c by b and store the result in register a.
Shift the value im by b and store the result in register a.
Muliply the values in registers b and c, store the result in register a.
Multiply the value in register b and the value im, store the result in register a.
Shift the value in register c by b and store the negation of the result in register a.
Shift the value im by b and store the negation of the result in register a.
Bitwise OR the values in registers b and c, store the (integer) remainder in register a.
Bitwise OR the value in registers b and the value im, store the (integer) remainder in register a.
Load register a with the word value stored in register b.
Add im to the contents of register b and store the result in register b.
Pseudo instructions.
Read an integer variable from standard input and store the value in register a.
Set the program counter to the value in register c.
Register numbers (0-31).
Register numbers (0-31). Program counter is R28.
Store the least-significant byte of the contents of register a to memory at the address given by the contents of register b plus the value im.
Store the contents of register a to memory at the address given by the contents of register b plus the value im.
Subtract the values in registers b and c, store the result in register a.
Subtract the value in register b and the value im, store the result in register a.
Branch target label We call this Target rather than Label to avoid a name clash with the Label class in RISCTree
Write a decimal representation of the value in register c to standard output.
Write a hexadecimal representation of the value in register c to standard output.
Bitwise XOR the values in registers b and c, store the (integer) remainder in register a.
Bitwise XOR the value in registers b and the value im, store the (integer) remainder in register a.
Write a newline to standard output.
Pretty-print a list of assembly code instructions to an emitter
Instruction set architecture for a simple RISC machine.