The code sequence that is being assembled.
Emit a RISC instruction.
Emit a comment.
Encode the given RISC program by emitting the prologue, then the encoding of each of the program's instructions, then the epilogue.
First and last temporary registers
Generate a brand new target label.
Generate a brand new target label. Shares counter with the transformation phase so that labels are unique.
Return the raw assembler code
Compute the final code sequence.
Compute the final code sequence. Compared to the one in the code buffer, symbolic labels are resolved into numeric displacements and all pseudo-instructions (comments and labels) are stripped before the code is returned.
Local register to use for base address of memory block.
Register allocation - we use an attribute grammar to implement a stack style allocation of registers.
Register allocation - we use an attribute grammar to implement a stack style allocation of registers. Unless a specific node type is handled by a special case, this attribution assumes that the children of each node will be evaluated in left to right order.
Reset the code cache
Translate RISC programs into RISC assembly code. Completes the code generation (e.g., by allocating registers). The resulting code is made available as a list of RISC machine instructions.