c

org.kiama.example.obr

RISCEncoder

class RISCEncoder extends AnyRef

Translate RISC programs into RISC assembly code. Completes the code generation (e.g., by allocating registers). The resulting code is made available as a list of RISC machine instructions.

Source
RISCEncoder.scala
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Instance Constructors

  1. new RISCEncoder()

Value Members

  1. final def !=(arg0: Any): Boolean
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  2. final def ##(): Int
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  3. final def ==(arg0: Any): Boolean
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  4. final def asInstanceOf[T0]: T0
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  5. def clone(): AnyRef
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    protected[java.lang]
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    @throws( ... )
  6. val code: Builder[Assembler, Seq[Assembler]]

    The code sequence that is being assembled.

  7. def emit(instr: Assembler): Unit

    Emit a RISC instruction.

  8. def emitcomment(text: String): Unit

    Emit a comment.

  9. def encode(p: RISCProg): Unit

    Encode the given RISC program by emitting the prologue, then the encoding of each of the program's instructions, then the epilogue.

  10. final def eq(arg0: AnyRef): Boolean
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  11. def equals(arg0: Any): Boolean
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  12. def finalize(): Unit
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  13. val firsttemp: Int

    First and last temporary registers

  14. def gentarget(): Label

    Generate a brand new target label.

    Generate a brand new target label. Shares counter with the transformation phase so that labels are unique.

  15. final def getClass(): Class[_]
    Definition Classes
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  16. def getassem: AssemCode

    Return the raw assembler code

  17. def getcode: Code

    Compute the final code sequence.

    Compute the final code sequence. Compared to the one in the code buffer, symbolic labels are resolved into numeric displacements and all pseudo-instructions (comments and labels) are stripped before the code is returned.

  18. def hashCode(): Int
    Definition Classes
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  19. final def isInstanceOf[T0]: Boolean
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  20. val lasttemp: Int
  21. val memreg: Int

    Local register to use for base address of memory block.

  22. final def ne(arg0: AnyRef): Boolean
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  23. final def notify(): Unit
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  24. final def notifyAll(): Unit
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  25. val reg: (RISCTree) ⇒ RegNo

    Register allocation - we use an attribute grammar to implement a stack style allocation of registers.

    Register allocation - we use an attribute grammar to implement a stack style allocation of registers. Unless a specific node type is handled by a special case, this attribution assumes that the children of each node will be evaluated in left to right order.

  26. def resetcode(): Unit

    Reset the code cache

  27. final def synchronized[T0](arg0: ⇒ T0): T0
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  28. def toString(): String
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  29. final def wait(): Unit
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  30. final def wait(arg0: Long, arg1: Int): Unit
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  31. final def wait(arg0: Long): Unit
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